This invention relates to a semiconductor test system having a large number of contactors for establishing electrical connection with a semiconductor device under test, and more particularly, to a probe contact system having a planarity adjustment mechanism for adjusting distances between tips of the contactors and contact targets such as contact pads of the semiconductor wafer to be tested.
In testing high density and high speed electrical devices such as LSI and VLSI circuits, a high performance contact structure provided on a probe card must be used. A contact structure is basically formed of a contact substrate having a large number of contactors or probe elements. The contact substrate is mounted on a probe card for testing LSI and VLSI chips, semiconductor wafers, burn-in of semiconductor wafers and dice, testing and burn-in of packaged semiconductor devices, printed circuit boards and the like.
In the case where semiconductor devices to be tested are in the form of a semiconductor wafer, a semiconductor test system such as an IC tester is usually connected to a substrate handler, such as an automatic wafer prober, to automatically test the semiconductor wafer. Such an example is shown in FIG. 1 in which a semiconductor test system has a test head 100 which is ordinarily in a separate housing and electrically connected to the test system with a bundle of cables 110. The test head 100 and a substrate handler 400 are mechanically as well as electrically connected with one another with the aid of a manipulator 500 which is driven by a motor 510. The semiconductor wafers to be tested are automatically provided to a test position of the test head 100 by the substrate handler 400.
On the test head 100, the semiconductor wafer to be tested is provided with test signals generated by the semiconductor test system. The resultant output signals from the semiconductor wafer under test (IC circuits formed on the semiconductor wafer) are transmitted to the semiconductor test system. In the semiconductor test system, the output signals are compared with expected data to determine whether the IC circuits on the semiconductor wafer function correctly or not.
In FIG. 1, the test head 100 and the substrate handler 400 are connected through an interface component 140 consisting of a performance board 120 (shown in FIG. 2) which is a printed circuit board having electric circuit connections unique to a test head""s electrical footprint, coaxial cables, pogo-pins and connectors. In FIG. 2, the test head 100 includes a large number of printed circuit boards 150 which correspond to the number of test channels (test pins) of the semiconductor test system. Each of the printed circuit boards 150 has a connector 160 to receive a corresponding contact terminal 121 of the performance board 120. A xe2x80x9cfrogxe2x80x9d ring 130 is mounted on the performance board 120 to accurately determine the contact position relative to the substrate handler 400. The frog ring 130 has a large number of contact pins 141, such as ZIF connectors or pogo-pins, connected to contact terminals 121, through coaxial cables 124.
As shown in FIG. 2, the test head 100 is placed over the substrate handler 400 and mechanically and electrically connected to the substrate handler through the interface component 140. In the substrate handler 400, a semiconductor wafer 300 to be tested is mounted on a chuck 180. In this example, a probe card 170 is provided above the semiconductor wafer 300 to be tested. The probe card 170 has a large number of probe contactors (such as cantilevers or needles) 190 to contact with contact targets such as circuit terminals or contact pads in the IC circuit on the semiconductor wafer 300 under test.
Electrical terminals or contact receptacles (contact pads) of the probe card 170 are electrically connected to the contact pins 141 provided on the frog ring 130. The contact pins 141 are also connected to the contact terminals 121 of the performance board 120 with the coaxial cables 124 where each contact terminal 121 is connected to the printed circuit board 150 of the test head 100. Further, the printed circuit boards 150 are connected to the semiconductor test system through the cable 110 having, for example, several hundreds of inner cables.
Under this arrangement, the probe contactors 190 contact the surface (contact targets) of the semiconductor wafer 300 on the chuck 180 to apply test signals to the semiconductor wafer 300 and receive the resultant output signals from the wafer 300. The resultant output signals from the semiconductor wafer 300 under test are compared with the expected data generated by the semiconductor test system to determine whether the IC circuits on the semiconductor wafer 300 performs properly.
A large number of contactors must be used in this type of semiconductor wafer test, such as from several hundreds to several thousands. In such an arrangement, it is necessary to planarize the tips of the contactors so that all of the contactors contact the contact targets at substantially the same time and same pressure. If planarization is not achieved, some contactors establish electrical connections with corresponding contact targets while other contactors fail to establish electrical connections, which is impossible to accurately test the semiconductor wafer. To completely connect all of the contactors to the contact targets, the semiconductor wafer must be further pressed against the probe card. This may physically damage semiconductor dice which receive excessive pressure by the contactors.
U.S. Pat. No. 5,861,759 shows an automatic probe card planarization system to planarize a first plane defined by a plurality of contact points of a probe card and relative to a second plane defined by a top surface of a semiconductor wafer supported on a prober. A camera is used to measure the height of at least three selected contact points on the probe card relative to the plane of wafer. Based on the measured values, the position of the first plane relative to the second plane is calculated.
With that information and the geometry of the prober and tester, the height variations necessary for the two height variable points are made to planarize the first plane relative to the second plane. This conventional technology requires a camera for visualizing the height of the contact points, resulting in increase in cost and decrease in reliability of the overall system.
U.S. Pat. No. 5,974,662 shows a method of planarizing tips of probe elements of a probe card assembly. The probe elements are mounted directly on a space transformer (contact substrate). It is so configured that the orientation of the space transformer, and thus the orientation of the probe elements, can be adjusted without changing the orientation of the probe card. In this method, an electrically conductive metal plate (virtual wafer) is provided in stead of the target semiconductor wafer as a reference plane. A cable and a computer are also provided in such a way that a computer display shows whether a conductive path is created or not for each probe tip relative to the metal plate by for example, white and black dots.
Based on the visual image on the display, the planarity of the probe tips is adjusted by rotating differential crews so that all of the probe tips make substantially simultaneous contact with the metal plate. Because this conventional technology uses a conductive metal plate to establish conductive path for all of probe elements, it requires an extra time to mount the metal plate and replace the same with the target semiconductor wafer. Further, because this method needs a computer and a display to illustrate the states of contact or non-contact of the probe element, an overall cost has to be increased.
Under the circumstances, there is a need in the industry to incorporate a more simple and economical way in a probe contact system to adjust the planarity of the contactors with respect to the surface of the semiconductor wafer.
Therefore, it is an object of the present invention to provide a probe contact system having a planarity adjustment mechanism for adjusting distances between tips of contactors and a surface of a semiconductor wafer under test.
It is another object of the present invention to provide a probe contact system having a planarity adjustment mechanism and a contact structure mounted on a probe card wherein the contact structure is formed of a contact substrate on which a large number of contactors are mounted.
It is a further object of the present invention to provide a probe contact system having a planarity adjustment mechanism for adjusting distances between a contact substrate and a semiconductor wafer under test so that all of contactors on the contact substrate contact the surface of the semiconductor wafer at the same time.
It is a further object of the present invention to provide a probe contact system having a planarity adjustment mechanism for adjusting distances between a contact substrate and a semiconductor wafer under test so that each contactor exerts an identical pressure against the surface of the semiconductor wafer when brought into contact with the semiconductor wafer.
In the present invention, a planarity adjustment mechanism for a probe contact system includes a contact substrate having a large number of contactors mounted on a surface thereof, a probe card for establishing electrical communication between the contactors and a test head of a semiconductor test system, connection means for fixedly connecting the contact substrate with the probe card, a probe card ring mounted on a frame of the probe contact system for mounting the probe card on an inner area thereof, and a plurality of shims provided between the probe card and the probe card ring at three or more locations wherein a number of shims at each of the locations is adjusted so that distances between tips of the contactors and surfaces of the contact targets become identical to one another.
In a further aspect, the planarity adjustment mechanism further includes a conductive elastomer provided between the contact substrate and the probe card. Preferably, the planarity adjustment mechanism of the present invention further includes a gap sensor for measuring a gap between the contact substrate and a semiconductor wafer to be tested or a reference plate (target substrate). The gap sensor determines the gap between the contact substrate and the target substrate by measuring capacitance between the gap sensor and an opposing electrode.